Details
The board level drop test method is intended to evaluate and compare drop performance of surface mount electronic components for handheld electronic products in an accelerated test environment, where excessive flexure of a circuit board causes product failure.
The popular use of mobile electronic devices, with increased interconnections accompanying more advanced functions, and decrease in interconnection strength caused by finer connections have resulted in more demanding environments for electronic devices in
terms of reliability and quality assurance. Mobile phones, laptops and other mobile devices are particularly prone to drop impact during use, which not only causes mechanical failures in the device housing but also create electrical failures in the internal
PCB assemblies, where failure modes could range from trace cracking on the board, cracking of solder interconnections between the components and the board, and the component cracks. The course familiarizes the attendees with standardization of the test board
and test methodology to provide a reproducible and comparable assessment of the drop test performance between surface mounted components while duplicating failure modes observed during product level test. The method is applicable to both area-array and perimeter-leaded
surface mounted packages. Finite element simulation of the board level drop test will also be taught using a commercial FEA software, together with how the results could be analyzed and performance compared across different products.
More Course Dates:
TBA
Copy the link to your browser for Course Brochure:
http://www.wizlogix.com/edm/JEDEC_Drop_Test/
Training Grants Available! Email us at [email protected] or Call us at +65 6272 6366 for more
information & registration!
Outline
Course outline
- Purpose of JESD22-B111
- Apparatus and Instrumentation Requirements
- Test Components and Board – Preferred construction & design, test board size, layout and component locations
- Test Procedures – Pre-test characterization & drop testing, failure criteria
- Failure Analysis and Reporting
- How to conduct/perform drop test simulation in FEA?
- Important aspects of drop test modeling setup
- Workshop 1: Jedec board model development,
- Workshop 2: Jedec board level drop test – post visualization, comparison of FE results with test
Who should attend?
Product reliability engineers, Product designers, R&D engineers, FEA engineers, engineers interested to know industry standards for board level drop reliability.
Speaker/s
Senior Consultant Overview Interests in research pertaining to microelectronic reliability, solder characterization (mechanical and microstructural) and chip fabrication.
Interests in research pertaining to defence – with topics ranging from blast, ballistics, infrastructure reliability, acoustics, protection of personnel and infrastructure, new material development.
Adept in CAD modeling & simulation (Explicit, Standard, Heat Transfer – Transient/Steady State, Thermal Stress, Modal Analysis, Parametric Modeling, Modeling of Failure, Sub-Modeling, CFD, CEL, SPH, Adaptive Remeshing, Acoustics Analysis) of structures & materials. Interests in simulation techniques such as XFEM, FSI.
Experienced in Lab setup and management, various testing techniques, Material Characterization, Metallurgy and Failure Analysis Developed various full undergraduate modules and laboratory lessons, and also provided numerous technical courses as a trainer.
Special Offer
Group Discount
A group discount will be awarded if a group of 3 or more participants register. The fees will be lowered to $1,099 per pax.
- In 2004, Wizlogix invested in high-end EDA tools to be used for in-house layout design services and explored into additional services such as PCB prototyping fabrication and assembly.
- In 2007, the Wizlogix Training Hub was established. Working with renowned trainers internationally, we aim to provide technical competency courses and certification programs for local engineers.
- In 2009, we further expanded to specialize in quick turn prototyping, New Product Introduction (NPI) and High Mix Low Volume (HMLV) builds.
- With the aim of expanding like an MNC, Wizlogix embarked on improving employee engagement through HR Capability Programmes in 2011.
- In 2012, we became an IPC member to gear ourselves towards a worldwide industry standard in PCB qualities acceptance.
- By 2013, Wizlogix was involved in the PCB layout of a joint commercial satellite design and development project between DSO and NTU, and the satellite design for Singapore Technologies. They are now known as ST (Satellite System). Since then, we became part of the space ecosystem in the government’s efforts towards nurturing this new industry. ...
